After putting it off for quite some time, I have finally decided to expand on the
"6V6 SE UL Bias Optimization" by investigating some other tubes. I've started with the 6L6GC with a 5kΩ load.
In order to make the process somewhat simpler, I have built a small jig which allows me to test tubes at the bench without having to use my prototyping station. The jig looks like this:
Attachment:
Test Box.jpg
This test jig includes 1Ω sense resistors on the plate and screen so that I can measure element current, and it includes grid circuit loading (Rg = 470kΩ, Gs = 1kΩ). The two binding posts covered by the shield are for the cathode load. Here is the test setup just after I finished gathering data on the brand new JJ 6L6GC.
Attachment:
Test_Setuo.jpg
This data set proved somewhat different from the 6V6 data. In that data set, the distortion at each plate voltage showed a relatively well behaved progression. The 6L6 distortion data was all relatively low and there was no clear separation between plate voltage curves. Here are the plots of peak power out and THD vs bias voltage for the five different plate voltages investigated.
Attachment:
Power vs THD.png
In this plot you can see how the distortion really doesn't vary much by plate voltage, but does seem so show a slow increase with bias voltage. This got me to wondering about the overall signal chain distortion, so I decided to measure just the driver distortion.
Now, for a driver in this setup, I just grabbed a 4S preamp with a JJ ECC83S (12AX7) preamp tube. This was never intended to be a driver circuit outputting large voltages, so I thought the distortion measurements should tell me something interesting. So here is the measured distortion of just the signal generator and the 4S driving the grid resistor in the test jig.
Attachment:
Driver Distortion.png
On this plot you can also see a linear regression fit to the driver distortion as a function of drive voltage. This could easily be the reason for the increasing distortion in the THD plot above.
So I decided to back out the best fit curve of driver THD from the total measured THD to see what the residual distortion looks like. After removing the driver distortion, this is what was left for the residual power stage THD.
Attachment:
Estimated Power Stage Distortion.png
As can be seen in the plot, all the distortion numbers are below 1% at peak power out with an average of around 1/2%.
So the final takeaway at this point is that the choice of optimization points really doesn't depend on distortion. Regardless of the points chosen, the design should produce a nice clean output. Instead I'll be choosing the final points based on other factors like output power, plate and screen power dissipations, and required current draws. More data to come as I continue to digest this data set.
As always, comments and questions are more than welcome.
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